With development of a semiconductor technology in recent years, high-speed serialization of data transmission between LSIs has been performed. As an interface for serializing parallel data for transmission, outputting the serialized parallel data to a transmission line, and converting received serial data into parallel data, a circuit referred to as a so-called “SERDES” (SERializer and Deserializer) has been in wide spread used. The SERDES circuit will be described with reference to FIG. 7.
As shown in FIG. 7, the SERDES is configured by including a PLL (Phase Locked Loop) circuit that generates a clock signal which will be used inside the device, a transmit circuit 11, and a receive circuit 12.
The transmit circuit 11 includes a parallel-to-serial converting circuit 13 that serializes parallel data. The receive circuit 12 includes a clock and data recovery circuit 14 and a serial-to-parallel converting circuit 15. The clock and data recovery circuit 14 extracts from received serial data a clock synchronized with the received serial data, and outputs the extracted clock signal (recovery clock) and the data. The serial-to-parallel converting circuit 15 parallelizes the serial data. With respect to the clock and data recovery circuit, descriptions in Patent Document 1 and 2 are referred to.
Due to high speed data transmission between LSIs, degradation in a transmission line between the LSIs has become nonnegligible. The transmission line has a low-pass filter characteristic. Thus, a high frequency component of not less than a predetermined frequency is attenuated, and interference between temporally adjacent symbols (ISI: Inter Symbol Interference) is generated. Quality of an input data waveform in a receiver side LSI is therefore degraded.
In order to suppress this degradation caused by the ISI, a pre-emphasis driver circuit is used in a transmitter side LSI, and an equalizer circuit is used in the receiver side LSI.
An example of the pre-emphasis driver circuit is disclosed in Patent Document 3. An example of the equalizer circuit is disclosed in each of Patent Documents 4 and 5. The equalizer disclosed in Patent Document 5 is referred to as a “DFE” (Decision Feedback Equalizer).
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2002-190724A
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2005-5999A
[Patent Document 3]
JP Patent No. 3730607
[Patent Document 4]
JP Patent Kokai Publication No. JP-P2006-42339A
[Patent Document 5]
JP Patent Kokai Publication No. JP-A-10-198913